Integrated circuits, the key components in thousands of electronic products, are interconnected networks of electrical components. Fabricators typically build these circuits layer by layer on a semiconductive wafer, using techniques, such as doping, masking, and etching, to form and then connect thousands and even millions of microscopic transistors. The wafer is then diced to define individual circuits, commonly known as ICs or chips, which are ultimately tested to verify performance.
Some conventional test techniques use a special test circuit, called a test-access port (TAP), which is built into the integrated circuit. Most, if not all, TAPs are designed to function in compliance with a standard, referred to as IEEE (Institute of Electrical and Electronic Engineers) 1149.1-2001, entitled Standard Test Access Port and Boundary-Scan Architecture. The standard was originally developed by the Joint Test Action Group (JTAG) and TAPs that comply with it are often called JTAG ports.
TAPs are often used with automatic test equipment that feeds a test pattern of voltages into the integrated through pins of the TAP. The test equipment then reads out the actual logic states of the integrated circuit, comparing them against expected logic states. A mismatch of the actual and expected logic states indicates a circuit failure. In response to a failure, the test equipment holds the circuit in the failed condition, and reads out (or “dumps”) the state values for the entire circuit to memory in the test equipment for further detailed analysis by other specialized equipment.
One problem the present inventor recognized in using TAPs with automatic test equipment is that integrated circuits, such as microprocessors, have outgrown the capacity of some automatic test equipment to read in all the state values while also storing their test patterns and maintaining the circuit in a failed condition. In other words, the test patterns and related data for testing these circuits consume most of the memory in the test equipment, leaving insufficient space for programming the TAP and storing all the state values.
To address this problem, some troubleshooters have opted to expand the memory capacity of their automatic test equipment. However, because of the high operating frequencies of the test equipment, this memory expansion can be quite expensive, with the cost to expand some types of testers approaching a million dollars per tester.
Other troubleshooters have resorted to working around the problem by rerunning the test pattern many times and building the complete set of state values, piece by piece through a series of partial dumps. However, this approach is not only quite time consuming, but also potentially ineffective when used with some complex integrated circuits, such as microprocessors. Microprocessors can behave unpredictably at times and make it difficult, if not impossible, to repeat a failure as often as necessary to collect a complete set of state values. Thus, in some instances, troubleshooters could be left to resolve a failure using an incomplete set of state values, or worse yet without sufficient data to resolve the failure at all.
Accordingly, there is a need for other ways of overcoming the memory limitations of automatic test equipment.